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RT9941 1 ds9941-01 april 2011 www.richtek.com ordering information note : richtek products are : ` rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ` suitable for use in snpb or pb-free soldering processes. power management ics for handheld device applications z gps and pda z handheld devices general description the RT9941 is a complete power management ic (pmic) for handheld device platform. this pmic contains a fully integrated linear charger for a single cell lithium ion battery, five ldo linear regulators and two high efficiency buck converters, a comparator, a reset and an i 2 c serial interface to program one buck and one regulator output voltages as well as power on timing control for complete flexibility. the linear charger integrates ldo, mosfet pass element and thermal-regulation circuitry. the proprietary thermal- regulation circuitry limits the die temperature when fast charging or while exposed to high ambient temperatures, allowing maximum charging current without damaging the ic. the two step-down converters are optimized for small size inductor and high efficiency applications. they utilize a proprietary hysteretic pwm control scheme that switches with nearly fixed frequency and is adjustable, allowing the customer to trade some efficiency for smaller external component as desired. the ldo linear regulators provide high power supply rejection rate and have only 45 v rms of output noises for 100hz to 10khz frequency range to power noise sensitive rf sections. the RT9941 is available in wqfn-40l 5x5 package. features z z z z z charger ` ` ` ` ` adapter & battery two input with auto power dynamic path. ` ` ` ` ` pwr_in ldo support continuous 1.5a, peak 2a current ` ` ` ` ` 4.5v to 5.5v operation voltage range with max. input 18v from pwr_in pin ` ` ` ` ` switch well for ldo and charger power mosfet ` ` ` ` ` set charge current by iseta pin ` ` ` ` ` charge status indicator ` ` ` ` ` interrupt for pwr_in plug in/out time out and charger done. ` ` ` ` ` battery temperature monitoring z z z z z hysteretic buck ` ` ` ` ` buck 1 for ddr memory, adjustable voltage and 600ma output current ` ` ` ` ` buck 2 for pdn with 25mv/step i 2 c adjustable 800ma output current ` ` ` ` ` max. efficiency up to 90% z z z z z ldo ` ` ` ` ` ldo1 : 3.3v/500ma for i/o, default on ` ` ` ` ` ldo2 : 1.2v/80ma for pll, default on ` ` ` ` ` ldo3 : 1.2v/80ma for pre-core. i 2 c adiustable, sync. with buck2, default on ` ` ` ` ` ldo4 : 2.5v/50ma for avdd of usb, adc, tsc, default on ` ` ` ` ` ldo5 : 3.3v/50ma for avdd of usb, default on ` ` ` ` ` minimize the external component counts z z z z z other ` ` ` ` ` system reset ` ` ` ` ` low voltage detector ` ` ` ` ` i 2 c compatible interface ` ` ` ` ` power on timing control z z z z z rohs compliant and halogen free package type qw : wqfn-40l 5x5 (w-type) lead plating system g : green (halogen free and pb free) RT9941
RT9941 2 ds9941-01 april 2011 www.richtek.com typical application circuit pin configurations (top view) wqfn-40l 5x5 30 29 28 27 26 25 24 23 22 21 31 32 33 34 35 36 37 38 39 40 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 data batt batt fb1 pgnd1 lx1 vin1 lx2 pgnd2 fb2 nchg_s ts timer vout2 vin3 vout3 vout1 vin2 vout4 vout5 nint nlbo lbi gnd s2 s1 pwr_en pwr_in pwr_in pwr_id vsys vsys hp_pwr pwr_on pwr_hold clk gnd iseta npbstas isetu 41 nreset ts fb1 pgnd1 lx1 vin1 lx2 pgnd2 fb2 hp_pwr vout1 vout4 vin3 vout5 vin2 vout2 RT9941 npbstas pwr_on nchg_s timer iseta vout3 batt gnd v buck1 1.8v/600ma v buck2 1.2v/600ma l2 3 27 26 25 24 23 22 21 34 17, exposed pad (41) 11 6 10 5 9 8 28, 29 38, 39 33 12 7 pwr_en s2 s1 vsys nreset 20 35, 36 19 18 10f l1 ldo1 (s1 and s2 control) 500ma + to vin1, vin2, vin3 pwr_in +5v (adapter / usb) vsys vsys nint 14 13 lbi vsys 4 2 16 1 4.7f 100k v back1 4.7f 1f 1f 1f 1f 10f 4.7f 22f 2k (750ma) 0.1f 510 vsys 100k vsys 100k nlbo 15 vsys 100k 100k 39k 4.7f pwr_id 37 pwr_hold isetu 40 32 2.2h 200k 100k 120pf 2.2h 100k 100k 220pf 1f ldo2 (s1 and s2 control) 200ma ldo3 80ma ldo4 (i2c control) 50ma ldo5 (i2c control) 50ma 100k v back1 usb adapter ntc data 30 vsys 4.7k clk 31 vsys 4.7k r set 500ma 100ma c timer vsys vsys vsys rtc alarm wake up from cpu, up
RT9941 3 ds9941-01 april 2011 www.richtek.com pin no. pin name pin function 1 nchg_s this pin indicates the status of the battery charger. open drain output and active low. 2 iseta pwr_in charge current setting pin. 3 ts temperature sense pin. 4 timer charge time setting. 5 vout2 1.2v/80ma ldo regulator. 6 vin3 this pin must be shorted to vsys, vin1 and vin2. connect a 4.7 f cer amic capacitor from vin3 to gnd. 7 vout3 1.2v/80ma ldo regulator with 25mv/step adjustable. 8 vout1 3.3v/500ma ldo regulator. 9 vin2 must be shorted to vsys, vin1 and vin3. connect a 10 f ceramic capacitor from vin2 to gnd. 10 vout4 2.5v/50ma ldo regulator. 11 vout5 3.3v/50ma ldo regulator. 12 npbstas push-button status pin. this pin is used to inform the power good state to processor. open drain output and active low. 13 nreset this pin provides a 200ms reset signal during power-up to initialize a processor. open drain and active low. 14 nint this pin must be active low to inform processor the interrupt events happened, open drain output and active low. 15 nlbo low-battery indication. open drain output and active low. 16 lbi low-battery detection. this pin is used to monitor the vsys voltage and the internal reference voltage is 1v 17, 41 (exposed pad) gnd ground. the exposed pad must be soldered to a large pcb and connected to gnd for maximum power dissipation. 18 s2 ldo1 & ldo2 output voltage setting, directly connect vsys to pull high, gnd to pull low. 19 s1 ldo1 & ldo2 output voltage setting, directly connect vsys to pull high, gnd to pull low. 20 pwr_en buck2 & ldo2 enable pin from processor. 21 fb2 voltage feedback2. fb2 regulates to 0.6v nominal. 22 pgnd2 buck 2?s power ground. 23 lx2 inductor connection to the drains of the internal n- mosfets and p-mosfets. 24 vin1 this pin must be shorted to vsys, vin2, and vin3. connect a 10 f cer amic capacitor from vin1 to gnd. 25 lx1 inductor connection to the drains of the internal n-mosfets and p-mosfets. 26 pgnd1 buck 1?s power ground. 27 fb1 voltage feedback1. fb1 regulates to 0.6v nominal. 28,29 batt main battery supply input terminal. this pin delivers charging current and monitors battery voltage. 30 data data input/output for serial interface. 31 clk clock input for serial interface. 32 pwr_hold logic low signal from processor to turn off the pmu. functional pin description to be continued
RT9941 4 ds9941-01 april 2011 www.richtek.com function block diagram pin no. pin name pin function 33 pwr_on active high power on / off key input. this pin has an internal 2 a pull-down current to gnd. when the push button is closed, it is shorted to sys, not ground. this input is de-bounced with 320ms (typ). 34 hp_pwr logic high signals connection of hands free kit. this pin has an internal 2 a pull-down current to gnd. this input is de-bounced with 320ms (typ). 35,36 vs ys connect this pin to system with a minimum 22 f ceramic capacitor to gnd. this pin must be shorted to vin1, vin2, and vin3 37 pwr_id power source input detection pin. 38,39 pwr_in power source input. connect a 4.7 f ceramic capacitor from this pin to gnd. 40 isetu usb charge current setting pin. functional pin description on/off control & i 2 c interface li-lon linear charger control thermal shutdown uvlo buck1 reset buck2 ldo1 ldo2 ldo3 ldo4 320ms debounce hp_pwr fb1 pgnd1 lx1 lx2 pgnd2 fb2 nchg_s vout5 vout2 pwr_en vout1 vout3 iseta isetu pwr_id timer batt vout4 pwr_on pwr_hold nreset pwr_in vsys vin1 ldo5 vin3 vin2 buck1 ok 2a 320ms debounce 2a npbstas ts sw control circuit nint + - lbi 1v vsys nlbo data clk s2 s1 gnd
RT9941 5 ds9941-01 april 2011 www.richtek.com to be continued recommended operating conditions (note 4) z junction temperature range --------------------------------------------------------------------------- ? 40 c to 125 c z ambient temperature range --------------------------------------------------------------------------- ? 40 c to 85 c absolute maximum ratings (note 1) z pwr_in ---------------------------------------------------------------------------------------------------- 0v to 7v z pwr_hold, pwr_on, hp_pwr, data, clk, nchg_s, iseta, ts, timer, npbstas, nreset, nint, nlbo, lbi, s2, pwr_en, pwr_id ------------------------------ ? 0.3v to vsys + 0.3v z fb2, fb1, lx2, lx1 -------------------------------------------------------------------------------------- ? 0.3v to vin1 + 0.3v z vout2, vout3 ------------------------------------------------------------------------------------------- ? 0.3v to vin3 + 0.3v z vout1, vout4, vout5 ------------------------------------------------------------------------------- ? 0.3v to vin2 + 0.3v z vin1, vin2, vin3 ----------------------------------------------------------------------------------------- vsys ? 0.3v to vsys + 0.3v z batt, vsys ----------------------------------------------------------------------------------------------- 0v to 5.5v z isetu ------------------------------------------------------------------------------------------------------- ? 0.3v to pwr_in + 0.3v 6v z power dissipation, p d @ t a = 25 c wqfn-40l 5x5 ------------------------------------------------------------------------------------------- 2.778w z package thermal resistance (note 2) wqfn-40l 5x5, ja -------------------------------------------------------------------------------------- 36 c/w wqfn-40l 5x5, jc ------------------------------------------------------------------------------------- 7 c/w z junction temperature ------------------------------------------------------------------------------------ 150 c z lead temperature (soldering, 10 sec.) -------------------------------------------------------------- 260 c z storage temperature range --------------------------------------------------------------------------- ? 65 c to 150 c z esd susceptibility (note 3) hbm (human body mode) ----------------------------------------------------------------------------- 2kv mm (ma chine mode) ------------------------------------------------------------------------------------- 200v note 1. stresses beyond those listed under ? absolute maximum ratings ? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note 2. ja is measured in the natural convection at t a = 25 c on a high effective four layers thermal conductivity test board of jedec 51-7 thermal measurement standard. the case point of jc is on the expose pad for the package. note 3. devices are esd sensitive. handling precaution is recommended. note 4. the device is not guaranteed to function outside its operating conditions.
RT9941 6 ds9941-01 april 2011 www.richtek.com electrical characteristics parameter symbol conditions min typ max unit system operating range input supply voltage v in without pwr_in 3.3 -- 5.5 v shutdown supply current i sh dn v batt = 4.2v, vout1 to 5, lx1, lx2 to ground. 4 10 15 a sleep mode supply current v batt = 3.7v, pwr_en = l, only buck1, ldo1, ldo3 turn on -- 120 200 a deep sl eep mode s uppl y current v batt = 3.7v -- 100 -- a system voltage lockout v sys rising -- 3.2 -- v under voltage lockout v sys falling -- 2.5 -- v thermal shutdow n threshold -- 160 -- c hystersis -- 10 -- c logic and control inputs input low level pwr_hold, pwr_on, hp_pwr, data, clk, pwr_en, pwr_id -- -- 0.4 v input high level pwr_hold, pwr_on, hp_pwr, data, clk, pwr_en, pwr_id 1.5 -- -- v input current pwr_hold, data, clk, pwr_en ? 1 -- 1 a pwr_on pull-down current to gnd pwr_on = 0.4v -- 2 -- a hp_pwr pull-down current to gnd hp_pwr = 0.4v -- 2 -- a pwr_on, hp_pwr de-bounce filter -- 320 -- ms nint, npbstas, nreset, nlbo pull down voltage source c urrent = 5ma -- 65 -- mv (v batt = 3.7v, c sys+ vinx = 47 f, c batt = 4.7 f, t a = 25 c, unless otherwise specified) electrical characteristics (general)
RT9941 7 ds9941-01 april 2011 www.richtek.com parameter symbol conditions min typ max unit output adjustable range 0.6 2.5 v fb threshold voltage v fb1 falling 0.582 0.6 0.618 v fb1 threshold line regulation v in = 2.7v to 5.5v -- 1.5 -- %/v fb1 threshold voltage hysteresis -- 12 -- mv p-mosfet switch 1000 1500 2000 current limit i lim n-mosfet switch -- 700 -- ma p-mosfet switch, i lx = ? 40ma -- 0.3 -- on-resistance n-mosfet switch, i lx = 40ma -- 0.38 -- rectifier off current threshold -- 30 -- ma (v batt = 3.7v, c sys+ vinx = 47 f, c batt = 4.7 f, t a = 25 c, unless otherwise specified) electrical characteristics (buck converter 1) electrical characteristics (buck converter 2) parameter symbol c onditions min typ max unit output adjustable range v ref -- 2.5 v default fb2 threshold voltage v fb2 falling 0.582 0.6 0.618 v fb2 threshold line regulation v in = 2.7v to 5.5v -- 1.5 -- %/v fb2 threshold voltage hysteresis -- 12 -- mv p-mosfet switch 1000 1500 2000 current limit i lim n-mosfet switch -- 700 -- ma p-mosfet switch, i lx = ? 40ma -- 0.4 -- on-resistance n-mosfet switch, i lx = 40ma -- 0.4 -- rectifier off current threshold -- 30 -- ma programmable fb2 voltage v fb2 falling 0.5 -- 0.7 v each programmable fb2 voltage step -- 12.5 -- mv (v batt = 3.7v, c sys+ vinx = 47 f, c batt = 4.7 f, t a = 25 c, unless otherwise specified)
RT9941 8 ds9941-01 april 2011 www.richtek.com parameter symbol conditions min typ max unit output voltage v ou t1 l load = 200ma & v in = 3.7v 3.201 3.3 3.399 v output current i out -- -- 200 ma current limit i lim v out1 = 0v -- 500 850 ma dropout voltage v drop l load = 200ma -- 150 -- mv line regulation v out1 + 0.4v v batt = v in1 5.5v, i load = 200ma -- 2.4 -- mv load regulation v in1 = 3.7v, 50 a < i load < 200ma -- 25 -- mv power supply rejection. v out / v in f = 10hz ? 10kh z, c ou t = 1 f, v out > 2.5v, i load = 30ma -- 60 -- db (v batt = 3.7v, c sys+ vinx = 47 f, c batt = 4.7 f, t a = 25 c, unless otherwise specified) electrical characteristics (vout1 (ldo1) ) note : all output capacitors are ceramic and x7r/x5r type. parameter symbol c onditions min typ max unit output voltage v out2 l load = 80ma & v in = 3.7v 1.164 1.2 1.236 v output current i out -- -- 80 ma current limit i lim v out2 = 0v -- 400 -- ma line regulation v out2 + 0.4v v batt = v in1 5.5v, l load = 80ma -- 2.4 -- mv load regulation v in1 = 3.7v, 50 a < l load < 80ma -- 25 -- mv power supply rejection. v out / v in f = 10hz ? 10khz ,c out = 1 f l load = 30ma -- 60 -- db (v batt = 3.7v, c sys+ vinx = 47 f, c batt = 4.7 f, t a = 25 c, unless otherwise specified) electrical characteristics (vout2 (ldo2) ) parameter symbol conditions min typ max unit output voltage v out3 l load = 80ma & v in = 3.7 v 1.164 1.2 1.236 v output current i out -- -- 80 ma current limit i lim v out3 = 0v -- 400 -- ma line regulation v out3 + 0.4v v ba tt = v in1 5.5v, l load = 80ma -- 2.4 -- mv load regulation 50 a < l load < 80ma -- 25 -- mv power supply rejection. v out / v in f = 1khz ,c out = 1 f l load = 30ma -- 60 -- db note : all output capacitors are ceramic and x7r/x5r type. (v batt = 3.7v, c sys+ vinx = 47 f, c batt = 4.7 f, t a = 25 c, unless otherwise specified) electrical characteristics (vout3 (ldo3) ) note : all output capacitors are ceramic and x7r/x5r type.
RT9941 9 ds9941-01 april 2011 www.richtek.com parameter symbol conditions min typ max unit output voltage v out4 l load = 50ma & v in = 3.7 v 2.425 2.5 2.575 v output current i out -- -- 50 ma current limit i lim v out4 = 0v -- 400 -- ma dropout voltage v drop l load = 50ma -- 50 -- mv line regulation v out4 + 0.4v v batt = v in1 5.5v, l load = 50ma -- 2.4 -- mv load regulation 50 a < l load < 50ma -- 25 -- mv power supply rejection. v out / v in f = 1khz , c out = 1 f, l load = 30ma -- 60 -- db (v batt = 3.7v, c sys+ vinx = 47 f, c batt = 4.7 f, t a = 25 c, unless otherwise specified) electrical characteristics (vout4 (ldo4) ) note : all output capacitors are ceramic and x7r/x5r type. par ameter symbol condit ions mi n typ max unit output voltage v out5 l load = 50ma & v in = 3.7 v 3.201 3.3 3.399 v output current i out -- -- 50 ma current limit i lim v out5 = 0v -- 400 -- ma dropout voltage v drop l load = 50ma -- 50 -- mv line regulation v out5 + 0.4v v batt = v in1 5.5v, l load = 50ma -- 2.4 -- mv load regulation 50 a < l load < 50ma -- 25 -- mv power supply rejection. v out / v in f = 1khz, c ou t = 1 f, l load = 30ma -- 60 -- db (v batt = 3.7v, c sys+ vinx = 47 f, c batt = 4.7 f, t a = 25 c, unless otherwise specified) electrical characteristics (vout5 (ldo5) ) note :all output capacitors are ceramic and x7r/x5r type.
RT9941 10 ds9941-01 april 2011 www.richtek.com parameter symbol conditions min typ max unit input voltage range and input current pwr_in input operation voltage range 4.5 -- 5.5 v pwr_id current -- -- 100 a isetu pull high current i setu = 0v -- 0.5 -- a pwr_in standby current v batt = 4.2v -- 300 500 a pwr_in uvp current v pwr_ in = 4v, v batt = 3v -- 150 250 a pwr_in uvp voltage -- 3.7 -- v i setu = h -- 450 500 pwr_id = h i setu = l -- -- 100 pwr_in current limit pwr_id = l -- 2300 -- ma voltage r egulation batt regulation voltage i batt = 60ma 4.158 4.2 4.242 v system regulation voltage 4.8 5 5.2 v pwr_in power fet r ds(on) i ac = 1a -- 350 -- m system to battery r ds(on) -- -- 150 m pwr_in to sys switch turn on v pwr_ in ? v batt -- 150 -- mv current regulation iseta set voltage (fast charge phase) v batt = 3.5v -- 2.5 -- v full charge setting range 100 -- 1200 ma timer timer pin source current v timer = 2v -- 1 -- a pre-charge fault time c time r = 0.1 f -- 2460 -- s charge fault time c timer = 0.1 f -- 19700 -- s precharge batt pre-charge threshold -- 2.8 -- v batt pre-charge threshold hysteresis -- 100 -- mv pre-charge current v batt < batt pre- charge thresho ld -- 10 -- % recharge threshold batt re-c harge falling threshold hysteresis v reg ? v batt -- 100 -- mv charge termination detection termination current ratio (default) iseta pin voltage -- 250 -- mv logic input/output nchg_s pull down voltage i/nchg_s = 5ma -- 300 -- mv (v pwr_in = 5v, v batt = 4v, t a = 25 c, unless otherwise specified) electrical characteristics (li-ion charger) to be continued
RT9941 11 ds9941-01 april 2011 www.richtek.com parameter symbol conditions min typ max unit nreset threshold with respect to buck2, rising -- 87 -- % nreset active time-out period from buck2 87% until reset = high -- 200 -- ms lbi reference voltage falling -- 1 -- v lbi hysteresis -- 50 -- mv lbi leakage current ? 1 -- 1 a parameter symbol conditions min typ max unit protection thermal regulation -- 125 -- c ts pi n s ource current v ts = 1.5v 94 100 106 a ts pin low threshold voltage 2.45 2.5 2.55 v ts pin high threshold voltage 0.485 0.5 0.515 v electrical characteristics (reset & low battery) (v batt = 3.7v, c sys+ vinx = 47 f, c batt = 4.7 f, t a = 25 c, unless otherwise specified)
RT9941 12 ds9941-01 april 2011 www.richtek.com typical operating characteristics power on v buck1 , v buck2 , v ldo1 , v ldo2 time (50 s/div) v ldo3 (1v/div) v ldo1 (500mv/div) v buck1 (2v/div) v buck2 (1v/div) power on v pwr_en , v ldo2 , v ldo4 , v ldo5 time (50 s/div) v ldo2 (2v/div) v pwr_en (5v/div) v ldo4 (200mv/div) v ldo5 (200mv/div) buck1 load regulation 1.66 1.7 1.74 1.78 1.82 1.86 1.9 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 output current (a) output voltage (v) v batt = 3.6v v buck1 = 1.8v v batt = 4v buck2 load regulation 1.08 1.11 1.14 1.17 1.2 1.23 1.26 1.29 1.32 0 0.1 0.2 0.3 0.4 0.5 0.6 output current (a) output voltage (v) v batt = 3.6v v buck2 = 1.35v v batt = 4v buck1 efficiency vs. output current 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 output current (a) efficiency (%) v batt=3.2v v batt=3.6v v batt=4v v buck1 = 1.8v buck2 efficiency vs. output current 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 output current (a) efficiency (%) v buck2 = 1.2v v batt=3.2v v batt=3.6v v batt=4v v batt = 4v v batt = 4v
RT9941 13 ds9941-01 april 2011 www.richtek.com i 2 c power on ldo4, ldo5 time (25 s/div) clk (5v/div) data (5v/div) ldo4 (2v/div) ldo5 (2v/div) i 2 c power off ldo4, ldo5 time (25 s/div) ldo4 (2v/div) date (5v/div) clk (5v/div) ldo5 (2v/div) normal to deep sleep mode time (100 s/div) v ldo3 (2v/div) v ldo2 (2v/div) v ldo4 (5v/div) v buck2 (5v/div) v ldo1 5v/div) v buck1 (2v/div) data (5v/div) v ldo5 5v/div) v batt = 4v, i out = 500ma buck1 output voltage ripple time (500ns/div) i lx1 (500ma/div) v buck1 (20mv/div) v lx1 (2v/div) normal to sleep mode time (10ms/div) v ldo2 (1v/div) v buck2 (1v/div) power on nreset response time (50ms/div) nreset (5v/div) v pwr_en (2v/div) v pwr_en (1v/div) v batt = 4v v batt = 4v v batt = 4v v batt = 4v v batt = 4v
RT9941 14 ds9941-01 april 2011 www.richtek.com ldo1 load regulation 3.26 3.28 3.3 3.32 3.34 3.36 0 0.04 0.08 0.12 0.16 0.2 output current (a) output voltage (v) buck frequency vs. input voltage 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5 input voltage (v) frequency (mhz) 1 i buck1 = i buck2 = 200ma buck1 buck2 v batt = 3.8v v batt = 4v, i out = 50ma to 500ma ldo1 load transient response time (100 s/div) i ldo1 (200ma/div) v ldo1 (50mv/div) v batt = 4v, i out = 0.1a to 0.6a buck2 load transient response time (250 s/div) i buck2 (200ma/div) v buck2 (50mv/div) v batt = 4v, i out = 500ma buck2 output voltage ripple time (500ns/div) i lx2 (500ma/div) v buck2 (20mv/div) v lx2 (2v/div) v batt = 4v, i out = 0.1a to 0.6a buck1 load transient response time (250 s/div) i buck1 (200ma/div) v buck1 (50mv/div)
RT9941 15 ds9941-01 april 2011 www.richtek.com charge current vs. r iseta 0 200 400 600 800 1000 1200 01.534.567.5910.51213.515 r iseta (k ? ) charge current (ma ) ldo psrr -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 100 1,000 10,000 100,000 frequency (hz) psrr (db) ldo1 dropout voltage vs. temperature 0 20 40 60 80 100 120 140 -40 -15 10 35 60 85 temperature (c) dropout voltage (mv) i out1 = 200ma v pwrin = 5v, v batt = 4v, pwrid = l, i sys = 0 to 2.4a charger power path at ac mode time (1ms/div) i batt (2a/div) v pwrin (2v/div) v sys (2v/div) v batt (2v/div) i pwrin (2a/div) i sys (2a/div) v pwrin v batt v sys i sys i pwrin i batt ldo1 ldo2 ldo3 ldo4 ldo5 i ldo1 = i ldo2 = i ldo3 = i ldo4 = i ldo5 = 30ma (k ) v pwrin = 5v, v batt = 4v, pwrid = l charge current vs. batt voltage 0 200 400 600 800 1000 1200 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 v batt (v) charge current (ma ) pwrid = l, r iseta = 1.5k pwrin = 4.5v pwrin = 5v v pwrin = 5v, v batt = 4v, pwrid = h, usbid = h charger power path at usb mode time (1ms/div) i batt (2a/div) v pwrin (2v/div) v sys (2v/div) v batt (2v/div) i pwrin (2a/div) i sys (2a/div) v pwrin v batt v sys i sys i pwrin i batt i sys = 0 to 2.4a
RT9941 16 ds9941-01 april 2011 www.richtek.com v pwrin = 5v, v batt = 3.8v, pwrid = l pwrin remove response time (250ms/div) i batt (2a/div) v pwrin (2v/div) v sys (2v/div) v batt (2v/div) i pwrin (2a/div) v pwrin v batt v sys i pwrin i batt v pwrin = 5v, v batt = 3.8v, pwrid = l pwrin insert response time (1ms/div) i batt (2a/div) v pwrin (2v/div) v sys (2v/div) v batt (2v/div) i pwrin (2a/div) v pwrin v batt v sys i pwrin i batt
RT9941 17 ds9941-01 april 2011 www.richtek.com application information i 2 c start and stop conditions both data and clk remain high when the bus is not busy. a high-to-low transition of data, while clk is high is defined as the start condition. a low-to-high transition of the data line while clk is high is defined as the stop condition. i 2 c acknowledge the number of data bytes between the start and stop conditions for the transmitter and receiver are unlimited. each 8- bit byte is followed by an acknowledge bit. the acknowledge bit is a high level signal put on data by the transmitter during which time the master generates an extra acknowledge related clock pulse. a slave receiver which is addressed must generate an acknowledge after each byte it receives. also a master receiver must generate an acknowledge after each byte it receives that has been clocked out of the slave transmitter. the device that acknowledges must pull down the data line during the acknowledge clock pulse, so that the data line is stable low during the high period of the acknowledge clock pulse (set-up and hold times must also be met). a master receiver must signal an end of data to the transmitter by not generating an acknowledge signal on the last byte that has been clocked out of the slave. in this case, the transmitter must leave data high to enable the master to generate a stop condition. i 2 c system configuration a device on the i 2 c bus which generates a ? message ? is called a ? transmitter ? and a device that receives the message is a ? receiver ? . the device that controls the message is the ? master ? and the devices that are controlled by the ? master ? are called ? slaves ? . i 2 c write command. the RT9941 writing address set 9c hex and write command and data to set internal register. type i : send the address and one command by i 2 c (figure 3). figure 1. i 2 c transmission flow in the RT9941 figure 2. i 2 c function block in the RT9941 scl sda a6 a5 a0 wa write command from the master. acknowledge from the slave. start 0 dx4 dx0 stop a acknowledge from the slave. start command from the master. 01 or 10 or 11 processor master RT9941 slave sdo scl sda vsys
RT9941 18 ds9941-01 april 2011 www.richtek.com table 1. register mapping table (underline is default) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 0 0 0 select group d1 0 0 1 ldo5 ldo4 ds_rdy pwr_ds[1] reserved 0 1 0 1 0 1 0 1 0 off on off on none deep sleep reco g nition po wer on enter to dee p slee p d2 0 1 0 vprog for ldo5 vprog for ldo5 vprog f or ldo4 vprog fo r ldo4 charger on/off z51 z50 z41 z40 0 1 off on d3 0 1 1 vprog for buck2, and ldo3 vprog for buck2, and ldo3 vprog for buck2, and ldo3 vprog for buck2, and ldo3 vprog for buck2, and ldo3 v4 v3 v2 v1 v0 v4 v3 v2 v1 v0 ldo3 output voltage (v) buck2 fb voltage (v) 0 0 0 0 0 1.0 0.5 0 0 0 0 1 1.025 0.5125 0 0 0 1 0 1.05 0.525 0 0 0 1 1 1.075 0.5375 0 0 1 0 0 1.1 0.55 0 0 1 0 1 1.125 0.5625 0 0 1 1 0 1.15 0.575 0 0 1 1 1 1.175 0.5875 0 1 0 0 0 1.2 (default) 0.6 (default) 0 1 0 0 1 1.225 0.6125 0 1 0 1 0 1.25 0.625 0 1 0 1 1 1.275 0.6375 0 1 1 0 0 1.3 0.65 0 1 1 0 1 1.325 0.6625 0 1 1 1 0 1.35 0.675 0 1 1 1 1 1.375 0.6875 1 x[3] x x x 1.4 0.7 note a : to enter deep sleep mode, ds_rdy and pwr_ds need to be set. note b : if charger on/off is ?0?, the charger will suspend in any external condition until this bit is ?1?. note c : ?x? means don?t care figure 3. i 2 c one command flow in the RT9941 a6 a5 a4 a3 a2 a1 a0 0 0 1 d14 0 1 0 0 1 1 d13 d12 d11 d10 d24 d23 d22 d21 d20 d34 d33 d32 d31 d30 address the 2nd word start 0 stop 9 w
RT9941 19 ds9941-01 april 2011 www.richtek.com figure 4. i 2 c two commands flow in the RT9941 group 0 ( bit 2 = 0, bit 1 = 0, bit 0 = 0) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ldo3 ldo2 ldo1 buck1 buck2 pwr_en 0 1 0 1 0 1 0 1 0 1 0 1 e1 0 1 off on off on off on off on off on none mask pwr_in in pwr_in out pwr_id reserved time out chg done 0 1 0 1 0 1 0 1 0 1 e2 1 0 none mask none mask none mask 1 (keep this bit =1) none mask none mas k i 2 c read command. the RT9941 reading address set 9d hex and read the interrupt status from internal register (figure 5). figure 5. i 2 c read command of the RT9941 table 2. the default status of interrupt registers for i 2 c reading (no pwr_in) register bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name pwr_in pwr_out pwr_id reserved time out 1 0 pwr_ds default 0 1 0 1 0 0 0 0 z41 z40 l do4 output voltage (v) 0 0 1.8 0 1 2.5 (default) 1 0 2.85 1 1 3.3 z51 z50 ldo5 output voltage (v) 0 0 1.2 0 1 1.5 1 0 3.0 1 1 3.3 (default) type ii : send address and two commands by i 2 c (figure 4). a6 a5 a4 a3 a2 a1 a0 0 0 0 x x g2 g1 g0 0 1 e15 e14 e13 e12 e11 e10 1 0 e25 e24 e23 e22 e21 e20 g2:0 = 3'b000 i 2 c address the 2nd word the 3rd word start stop stop 0 9 18 27 w g a5 a4 a3 a2 a1 a0 b7 b6 b5 b4 b3 b2 b1 b0 address read register start 1 9 stop 18 r
RT9941 20 ds9941-01 april 2011 www.richtek.com ldo1 & ldo2 voltage setting pin s1 and s2 are tri-stat input to set ldo1 and ldo2 voltage. connect to vsys directly to pull high and gnd to pull low. the voltage setting table is listed in table 3. power sequence if the pwr_in and vsys pin voltages are below the internal uvlo threshold, all ic blocks are disabled and the RT9941 is not operational. when an external power source or battery with voltage greater than the uvlo voltage threshold is applied to vsys pins, the internal RT9941 references are powered up and biasing internal circuits. when all the main internal supply rails are active, the RT9941 i 2 c registers are set to the power-up default values. if a power good fault is not present at the end of the power good check mode and then normal mode starts. in this mode of operation, the i 2 c registers define the RT9941 operation, and must be able to handle all issues regarding power on/off the handheld device. the pwr_on and pwr_hold pins determine the power on/off status of the handset. logic high on pwr_on pin is the normal way of powering up a handset. the pwr_on signal is held high for at least 320 ms; buck1, 2 and ldo1, 3 are turned on; when buck2 reaches 87% of its final value, a 200ms reset timer is started at after which nreset is asserted high, and then the handheld device processor is initialized and will assert pwr_hold high to maintain power on. this wrap around constitutes the pwr_on button can be released (return to low state) and the power remains on. if, however, pwr_on is released before the pwr_hold signal is asserted, then buck1, 2 and ldo1, 3 will be turned off. all output could be turned off by the processor asserting pwr_hold low, if pwr_on = low. the RT9941's default power output voltages for sirf titanii and a4 platform are listed in table 4 as following : table 3. ldo1 & ldo2 voltage setting s1 s2 ldo1 (v) ldo2 (v) l h 3.3 1.2 h l 2.8 1.2 h h 2.5 1.2 l f 1.8 1.2 f h 2.5 1.3 f f 1.8 1.3 h f 3.3 1.3 f l 2.5 1.0 l l 3.0 1.2 table 4. the RT9941 for samsung platform power terminology buck1 buck2 ldo1 ldo2 ldo3 ldo4 ldo5 control pin pwr_on pwr_en pwr_on pwr_en pwr_on i 2 c i 2 c default output voltage 1.8v 1.2v only auto start up in the first time by pwr_on 3.3v 1.2v 1.2v 2.5v only auto start up in the first time by pwr_en 3.3v only auto start up in the first time by pwr_en sirf titan ii a4 vddio_mem vdd_pdn vddio vddio_pll vdd_pll vdd_pre vdda2v5_usb, vddio_tsc vdda_tsc, vref_adc vdda3v3_ usb
RT9941 21 ds9941-01 april 2011 www.richtek.com figure 6. power and interface module i 2 c decoder i 2 c registers and non- volatile memory interrupt controller system and battery charger control logic sequencing & operating mode setting host processor clk data nint nreset npbstas pwr_hold hp_pwr pwr_on vsys vmem vsys pwr_in batt pwr_en vsys vsys ldo1, 2 voltage setting by pin s1 and s2 ldo2 and buck2 can be turned on/off by the external pwr_en pin. the i 2 c will be activated if the buck1 is enabled. ldo 4,5 can be turn on by pwr_en pin in the first power on sequence. ldo 1, 2, 3, 4, 5 and buck1, 2 output voltages can turned on and off by i 2 c. ldo 3, 4, 5 and buck2 output voltages can be programmed by i 2 c. figure 7. RT9941 power on/off timing diagram pwr_on ldo3 buck1 ldo1 pwr_en ldo2 ldo4 ldo5 buck2 pwr_hold i 2 c: ldo4/5_en nreset 300ms 100s 100s 200ms vdd_pre vdd_io, vddio_pll vddio_mem, vref_mem vdd_pdn vdd_pll, vdda_pll vdda2v5_usb, vddio_tsc vdda_tsc, vref_adc vdda3v3_usb 10s 100s 300s
RT9941 22 ds9941-01 april 2011 www.richtek.com figure 8. RT9941 deep sleep mode timing diagram the relationship between i 2 c register and different mode setting is listed in table 5. table 5. different mode setting by pwr_ds and ds_rdy system mode pwr_ds ds_rdy normal mode (default status) 0 0 to enter deep sleep mode 1 1 power on from deep sleep mode 0 1 sleep mode the external host can set the RT9941 in sleep mode using the gpio configuration. in the sleep mode, change the pwr_en signal to set different output on/off status : 1. buck2 and ldo2 will be disabled when the pwr_en is turned off to enter the sleep mode. 2. when the pwr_en is turned on, the buck2 and ldo2 are enabled and the reset signal from the RT9941 remains high. deep sleep mode in deep sleep mode, an i 2 c register is used to control the RT9941 to turn off specific power output. to enter deep sleep mode operation, the RT9941 is needed to set i 2 c register bits, both ds_rdy = 1 and pwr_ds = 1. after the RT9941 receiving the command by i 2 c interface , it will just remain buck1 turn on and all the other power output will be turned off, the RT9941 output reset signal will be driven to low state to processor. if the pwr_on signal is set to high again, the RT9941 output will be waken up and recovered to the previous state. for recording this deep sleep mode wake up situation, the pwr_ds = 0 and ds_rdy keep high must be made to acknowledge the processor (figure 8). t2 buck1 nreset pwr_on t1 normal mode deep-sleep mode power on sequence power off sequence notes 1 : t1 at least 650s for internal lvr setting up time , is about 2ms to wait pll stable other time interval is dependen t on power stable. notes 2 : after wake up sequence from deep-sl eep mode, the power on sequence to normal mode is similar to when powering on init ially. ldo3 normal mode wake up sequence ldo1 i 2 c command set ds_rdy = 1 and pwr_ds = 1 set pwr_on to hi to wake up buck2
RT9941 23 ds9941-01 april 2011 www.richtek.com table 6. interrupt register table register name default function int event bit7 pw r _in 0 if pw r_in = hi, this bit will be set. yes bit6 pw r _ou t 1 if pw r_in= lo, this bit w ill be set. yes bit5 pw r _id 0 if pw r_in =h &pw r_id=h this bit will be set. ye s bit4 reserved 1 no bit3 time_out 0 this bit will be set if tim e out. yes bit2 chg_done 0 this bit will be set if charge done. yes bit1 ds_rdy 0 if pmu enter to deep sleep mode, this bit will be set. no bit0 pwr_ds 0 if pmu power on from deep sleep mode, this bit need to be set. no interrupt mode the RT9941 interruption controller monitors multiple system status parameters and signals to the host when one of the monitored parameters toggled, as a result of system status change. if the external interrupt event happened, the internal interrupt flag of the RT9941 will be triggered. the interrupt flag with no mask will set the nint to low state. the host processor receivers the active low signal and then try to read the interrupt register by i 2 c interface. the interrupt controller setting and function in register are listed in the table 6. if this internal interrupt event is set without mask, the interrupt controller will set nint to low if any interrupt behavior happened. then processor will be acknowledged by nint and then read register status by i 2 c interface. pmu will accept this read ok status and let the nint return to high (figure 9). if this internal interrupt register is set with mask, the interrupt controller will not set nint to low even external real interrupt event happened (figure 10). figure 9. interrupt without mask figure 10. interrupt with mask interrupt event clk data nint interrupt mask = 0 read ok interrupt event clk data nint interrupt mask = 1 set mask = 0 read ok
RT9941 24 ds9941-01 april 2011 www.richtek.com pwr_on & hp_pwr & npbstas connecting external signal such as head phone can start up the power sequence of power management circuit. when the RT9941 detects a hp_pwr rising edge signal and generates a over 320ms pulse. all RT9941 output will be turned on even the without recognizing pwr_on signal. the handheld device processor is initialized and will assert pwr_hold to high to maintain the RT9941 power remains on. this power on behavior is same as pwr_on signal asserted. npbstas signal is an inverter of pwr_on with 320ms de-bounced to inform soc or up that power on button has been pressed. pwr_on & hp_pwr & npbstas timing control diagram in the figure 11. figure 11. pwr_on & hp_pwr & npbstas timing diagram buck converters the RT9941 step-down converters are optimized for high efficiency over a wide load range, small external component size, low output ripple, and excellent transient response. the dc/dc converters also feature an optimized on-resistance internal mosfet switch and synchronous rectifier to maximize the efficiency and minimize the external components. the RT9941 utilizes a proprietary hysteretic pwm control scheme that switches with nearly fixed frequency, allowing the customer to trade some efficiency for smaller external component, as desired. if one buck converter is not used, please make lx = open, fb = in, and pgnd = gnd. figure 12. step-down converter block diagram nreset ldo3 buck2 ldo1 buck1 pwr_on hp_pwr npbstas 320ms 200ms pwr_hold lx logic + buffer + - fb pgnd vsys c in l c ff c out v out r1 r2 reference v ref current limit zero-current detection zc oc
RT9941 25 ds9941-01 april 2011 www.richtek.com setting the output voltage select an output voltage between 0.6v and 2.5v by connecting fb to a resistive voltage divider between lx and gnd. choose r2 for a reasonable bias current in the resistive divider. a wide range of resistor values is acceptable, but a good starting point is to choose r2 as 100k . then, r1 is given by : ( ) out fb1 r1 v1v r2 =+ below table is the default value of resistor and c ff for different output voltages. v buck (v) r1 (k) r2 (k) c ff (pf) 1.2 100 100 220 1.8 200 100 120 2.5 316 100 120 inductor selection the RT9941 step-down converters operate with inductors of 1 h to 4.7 h. low inductance values are physically smaller but require faster switching, which results in some efficiency loss. the inductor's dc current rating only needs to match the maximum load current of the application because the RT9941 step-down converters feature zero current overshoot during startup and load transients. the recommended inductor is 2.2 h. for optimum voltage positioning load transients, choose an inductor with dc series resistance in the 50m to 150m range. for higher efficiency at heavy loads (above 200ma) or minimal load regulation (but some transient overshoot), the resistance should be kept below 100m . for light load applications up to 200ma, much higher resistance is acceptable with very little impact on performance. output capacitor selection the output capacitor, c out , is required to keep the output voltage ripple small and to ensure the regulation loop stability. c out must have low impedance at the switching frequency. ceramic capacitors with x5r or x7r dielectric are highly recommended due to their characteristics of small size, low esr, and small temperature coefficients. due to the unique feedback network, the output capacitance can be very low. for most applications, a 4.7 f capacitor is sufficient. feedforward capacitor selection the feedforward capacitor, c ff , sets the feedback loop response, controls the switching frequency, and is critical in obtaining the best efficiency possible. choose a small ceramic x7r capacitor with value given by : select the closest standard value to c ff as possible. ff l c10 r1 = charger the RT9941 has an integrated charger with power path integrated mosfets. this topology, shown in the simplified block diagram (figure 13), enables the goal of using an external input power to run the system and charge the battery. the power path has single inputs that can be used to select either an external ac_dc adapter or usb port by pwr_id pin and different charging current by limitation. the RT9941 connects the end equipment main power rail and charges the battery pack by the batt pin. , where v fb1 is the feedback reference voltage (0.6v typ.)
RT9941 26 ds9941-01 april 2011 www.richtek.com the RT9941 charger uses current, voltage, and thermal control loops to charge and protect a single li+ battery cell. one enable input pwr_id pin is supplied to set charging current limits. during pre-charge and fast-charge phases, the charger output status is pulled low. as the battery voltage approaches 4.2v, the charging current is reduced. when the charging current drops below 10% of charging current setting and the battery voltage equals 4.2v, the nchg_s output pin goes high impedance, signaling a full battery and set the internal i 2 c register bit chg done. if the charger done is not masked, the interrupt flag will be trigged. at any time during charging, if the RT9941 internal i 2 c register bit, charger on/off, is clear. then the charger enters suspend mode, charging stops, and nchg_s goes high impedance. battery charge management function the RT9941 supports charging of single-cell li-ion battery packs. the charge process is executed in three phases: pre- charge (or preconditioning), constant current and constant voltage. a typical charge profile and flow chart are shown in figure 14 & 15. figure 14. typical charge profile figure 13. charger block diagram and required external components ldo vsys batt ts iseta nchg_s pwr_id usb/ac adapter pwr_in q1 q2 system power bus r set + ntc li battery cc/cv dynamic battery supplement current scaling and charger suspend power path control, system power and current limit selection precharge phase fast charge phase constant voltage phase & standby phase recharge phase 2.8v precharge threshold 4.2v recharge threshold 1/10 programmed charge current programmed charge current charge complete 4.1v
RT9941 27 ds9941-01 april 2011 www.richtek.com figure 15. charge flow chat power-path management the power path and charge management block operate independently of the other RT9941 circuits. internal circuits check battery parameters (pack temperature, battery voltage and charge current) and system parameters, setting the power path mosfets operating modes automatically. the RT9941 has integrated comparators that monitor the battery voltage, power input pin voltage and the sys pin voltage. the data generated by those comparators is used by the power path control logic to define which of the integrated power path switches is active. a typical auto power path management profile is shown in f igure 16 & 17. figure 16. typical power path management profile any state if vin < uvlo or vin > ovp or i 2 c = off or vin < batt power off state pfet = off no batt>2.8v yes pre-chg state ichg_pre = 0.1 x ichg_fast fast-chg state ichg_fast = 1000ma @r set = 1.5k ? check thermal temp.<125c charge done state ichg = 0a no yes yes yes batt < 4.1v 0.5v < ts < 2.5v no no ichg<0.1*ichg_fast yes no decrease ichg_fast temp.<125c uvlo > vin < ovp & i 2 c = on &vin > batt pwr_in sys 1a 0 -1a 2a 3a -2a -3a 5v 4.65v 4.2v 4.0v i batt i sys i pwr_in t1 t2 t3 t4 t5 t6 t7 batt 0v
RT9941 28 ds9941-01 april 2011 www.richtek.com the RT9941 powers the system while independently charging the battery. this feature reduces the charge and discharge cycles on the battery, allows for proper charge termination, and allows the system to run with an absent or defective battery pack. this feature gives the system priority on input power, allowing the system to power up with a deeply discharged battery pack. this feature works as follows: case 1: ac mode (pwr_id = low) in this case, the system load is powered directly from the ac adapter through the internal transistor q1 (figure 18). the output sys is regulated at 5.0 v. if the system load exceeds the capacity of the supply, the output voltage drops down to the battery's voltage. when in ac mode, the battery is charged through the switch q2 based on the charge rate set on the iseta input pin. this feature monitors the output voltage (system voltage) for input power loss due to brown outs, current limiting, or removal of the input supply. if the voltage on the vsys pin drops to a preset value(4.2v) due to a limited amount of input current, then the battery charging current is reduced until the vsys stops dropping. if the system continues increasing load to exceed the ac adapter capacity, the battery will start to discharge to vsys. figure 18. RT9941 powered by ac adapter figure 17. power path management flow chart ldo power path control, system power and current limit selection pwr_id pwr_in adapter from adapter vsys id v+ gnd v+ gnd q1 batt supply sys sys < batt (t8) ac supply sys & batt sys > batt (t1,t2,t6,t7) ac supply sys & batt reduce charge current sys = 4.2v > batt (t3,t5) ac & batt supply sys sys < batt (t4) no no no no no sys load > ac current limit ac current limit acok? ac current limit acok? acok? yes yes yes no no yes yes yes
RT9941 29 ds9941-01 april 2011 www.richtek.com case 2: usb mode (pwr_id = high) in this case, the system load is powered from a usb port through the internal switch q1 (figure 19). note that in this case, q1 regulates the total current to the 450ma level as selected on the input. the output, sys, is regulated to 5v. the system's power management is responsible for keeping its system load below the usb current. otherwise, the output drops (vsys) to the battery voltage; therefore, the system should have a low-power mode for usb power application. figure 19. RT9941 powered byusb port table 7. pwr_in input current and charger current-limit selection pwr_id pwr_in current limit expected input type charger current limit hi 450ma usb 450ma lo 2.3a ac adapter (2.5v/rset)*600 charge-current selection when powered from a usb port, the input current is available to 0.5 a. for ac-adapter input applications (pwr_id = low) requiring a different current requirement, set the charging current with an external resistor (r set ) from iseta to gnd. calculate charge current as follows : charge current = 2.5/ r set (k ) x 600 (ma) the RT9941 offers iseta pin to determine the ac charge rate from 100ma to 1a. charge-status output nchg_s is an open-drain output that indicates charger status and can be used with an external led. nchg_s goes low during charging. when vbat equals 4.2v and the charging current drops below 10% of the setting charge current, nchg_s goes high impedance and the RT9941 internal i 2 c register bit chg done will be set. connect a pull-up resistor between nchg_s and vsys to indicate charge status. soft-start to prevent input transients, the change rate of the charge current is limited when the charger is turned on or changes its current compliance. it takes approximately 1ms for the charger to go from 0ma to the maximum fast-charge current. temperature monitoring the RT9941 monitors the battery temperature by measuring the voltage between the ts and gnd pins. the RT9941 has an internal current source to provide the bias for most common 10k negative-temperature thermistor (ntc) with the battery. ldo power path control, system power and current limit selection pwr_id pwr_in usb vsys id vbus gnd vbus gnd q1 d+ d- usb port from pc or notebook
RT9941 30 ds9941-01 april 2011 www.richtek.com the RT9941 compares the voltage on the ts pin against the internal v ts thresholds to determine if charging is allowed. when the temperature outside the v ts thresholds is detected, the device immediately stops the charger. charging is resumed when the v ts is recovered to the operation range. however, the user may modify thresholds by adding external resistors to change biasing voltage. timer as a safety mechanism, the charger has a user programmable timer that monitors the pre-charge and fast charge time. this timer (charge safety timer) is started at the beginning of the pre-charge and fast charge period. the safety charge timeout value is set by the value of an external capacitor connected to the timr pin (c timr ), if pin timr is short to gnd, the charge safety timer is disabled. as c timr = 0.1 f, t fault is c timr (f) x 1.97 x 10 11 secs = 19700 secs and t prech = t fault /8 as timer fault, re-plug-in power or i 2 c on/off charger again can release the fault condition. sys output the RT9941 contains a sys output which can be regulated up to 5v. bypass sys to gnd with a 22 f or larger ceramic capacitor to improve the transient droops. when charging a battery, the load on sys is serviced first and the remaining available current goes to charge the battery. battery pre-charge during a charge cycle, if the battery voltage is below the v prech threshold and the RT9941 applies a pre-charge mode to the battery. this feature revives deeply discharged cells and protects battery life. the RT9941 internally determines the pre-charge rate as 10% of the fast charge current. thermal regulation the RT9941 features a thermal limit that reduces the charge current when the die temperature exceeds +125 c. as the temperature increases, the RT9941 features a junction temperature regulation loop. if the power dissipation of the ic results in a junction temperature greater than the thermal regulation threshold (125 c), the RT9941 throttles back on the charge current in order to maintain a junction temperature around the thermal regulation threshold (125 c). the RT9941 monitors the junction temperature, t j , of the die and disconnects the battery from the input if t j exceeds 125 c. this operation continues until junction temperature falls below the thermal regulation threshold (125 c) by the hysteresis level. this feature prevents the maximum power dissipation from exceeding typical design conditions. figure 21. connection of battery te mperature monitor with divider t2 t1 ntc ts ts t1 t2 ntc r(rr) vi rr r + = ++ temperature sense a + i ts ts 0.1uf to 10uf ntc v batt battery r t1 r t2 figure 20. connection of battery te mperature monitor ts ts vr100ua = temperature sense a + i ts ts 0.1uf to 10uf ntc v batt battery
RT9941 31 ds9941-01 april 2011 www.richtek.com thermal considerations for continuous operation, do not exceed absolute maximum operation junction temperature. the maximum power dissipation depends on the thermal resistance of ic package, pcb layout, the rate of surroundings airflow and temperature difference between junction to ambient. the maximum power dissipation can be calculated by following formula : p d(max) = ( t j(max) - t a ) / ja where t j(max) is the maximum operation junction temperature 125 c, t a is the ambient temperature and the ja is the junction to ambient thermal resistance. for recommended operating conditions specification of RT9941, where t j(max) is the maximum junction temperature of the die (125 c) and t a is the maximum ambient temperature. the junction to ambient thermal resistance ja is layout dependent. for wqfn-40l 5x5 packages, the thermal resistance ja is 36c/w on the standard jedec 51-7 four layers thermal test board. the maximum power dissipation at t a = 25 c can be calculated by following formula : p d(max) = ( 125 c - 25 c) / (36 c/w) = 2.778w for wqfn-40l 5x5 packages figure 22. lbi and nlbo application circuit figure 23. typical lbi rising and falling threshold voltage. capacitor selection connect a ceramic capacitor from pwr_in to gnd as close to the ic as possible for proper stability. for most applications, connect a 4.7 f ceramic capacitor from in to gnd as close to the ic as possible. linear regulators the RT9941 offers five integrated linear regulators, designed to be stable over the operating load range with the use of external ceramic capacitors. all the ldo have an on/off control which can be set by i2c commands and have integrated switches that discharge each output to ground when the ldo is turned off. the ldo 1, 3 will be turn on in the first time of pwr_on button be pressed and ldo2 will be turned on when pwr_en = 1. ldo 4, 5 need to be turned on/off by i 2 c command. the ldo4,5 also support four voltage setting by i2c control. ldo1 and ldo2 voltages are set by the s1, s2 pin, see table 3. low-battery detector nlbo is an open-drain output that typically connects to the batt fault input of the processor to indicate the battery has been removed or discharged. nlbo is typically pulled up to vsys. lbi monitors the input voltage (usually connect to vsys) and triggers the nlbo output (figure 22). nlbo is high impedance when the voltage from lbi exceeds the battery rising threshold vlbith =1.05v (typ.). nlbo is low when the voltage from lbi falls below the low-battery falling threshold vlbith =1v (typ) (figure 23). connecting lbi to two-resistor voltage divider to detect the external resistor embedded in a battery pack and is also used as a pack id function. when system first power up or back from deep sleep mode , lbi will check the vsys voltage. if vsys voltage is lower than setting voltage, system will not power up or wake up. if the low-battery-detector feature is not required, connect nlbo to ground and connect lbi to sys. + - sys nlbo 1v vsys lbi 1.05v 1v lbi nlbo
RT9941 32 ds9941-01 april 2011 www.richtek.com layout considerations for the best performance of the RT9941, the following pcb layout guidelines must be strictly followed. ` place the input and output capacitors as close as possible to the input and output pins. ` keep the main power traces as possible as wide and short. ` to minimize emi, the switching area connected to lx inductor should be smallest possible. ` place the feedback components as close as possible to the fb pin and keep these components away from the noisy devices. also, the feed forward capacitor c ff trace is sensitive to the magnetic field that the inductor generates. please keep the c ff trace away from the inductor and use a via and run the trace between ground layers. ` connect the gnd and exposed pad to a strong ground plane for maximum thermal dissipation and noise protection. figure 25. pcb layout guide the maximum power dissipation depends on operating ambient temperature for fixed t j (max) and thermal resistance ja . for RT9941 packages, the figure 24 of derating curves allows the designer to see the effect of rising ambient temperature on the maximum power allowed. 30 29 28 27 26 25 24 23 22 21 31 32 33 34 35 36 37 38 39 40 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 data batt batt fb1 pgnd1 lx1 vin1 lx2 pgnd2 fb2 nchg_s ts timer vout2 vin3 vout3 vout1 vin2 vout4 vout5 nint nlbo lbi gnd s2 s1 pwr_en pwr_in pwr_in pwr_id vsys vsys hp_pwr pwr_on pwr_hold clk gnd iseta npbstas isetu 41 nreset c batt r14 r13 r11 r10 c ff1 l1 c buck1 c in1 l2 c buck2 r13 r12 c ff2 buck1 buck2 r9 r8 r7 r6 r5 r4 c5 c4 c in2 c in3 c1 c3 c2 r2 r3 c6 r1 c pwr_in c sys high-current path should be made as short and wide as possible. place input and output capacitors (connected to the ground) as close as possible to the ic. connect the inductors, output capacitors, and feedback resistors as close to the ic as possible and keep the traces short, direct, and wide. keep the voltage feedback network very close to the ic, but away from inductor & lx. v sys v sys v sys v sys v sys gnd gnd gnd gnd gnd gnd gnd gnd figure 24. derating curves for RT9941 packages 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 0 25 50 75 100 125 ambient temperature (c) maximum power dissipation (w) wqfn-40l 5x5 four layers pcb
RT9941 33 ds9941-01 april 2011 www.richtek.com richtek technology corporation headquarter 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 fax: (8863)5526611 information that is provided by richtek technology corporation is believed to be accurate and reliable. richtek reserves the ri ght to make any change in circuit design, specification or other related things if necessary without notice at any time. no third party intellectual property infringemen t of the applications should be guaranteed by users when integrating richtek products into any application. no legal responsibility for any said applications is assumed b y richtek. richtek technology corporation taipei office (marketing) 5f, no. 95, minchiuan road, hsintien city taipei county, taiwan, r.o.c. tel: (8862)86672399 fax: (8862)86672377 email: marketing@richtek.com outline dimension symbol dimensions in millimeters dimensions in inches min max min max a 0.700 0.800 0.028 0.031 a1 0.000 0.050 0.000 0.002 a3 0.175 0.250 0.007 0.010 b 0.150 0.250 0.006 0.010 d 4.950 5.050 0.195 0.199 d2 3.250 3.500 0.128 0.138 e 4.950 5.050 0.195 0.199 e2 3.250 3.500 0.128 0.138 e 0.400 0.016 l 0.350 0.450 0.014 0.018 w-type 40l qfn 5x5 package note : the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. det ail a pin #1 id and tie bar mark options 1 1 2 2 d e d2 e2 l b a a1 a3 e 1 see detail a

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